Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events

Authors

DOI:

https://doi.org/10.24203/ajet.v6i5.5464

Keywords:

Semiconductor packages, IC, QFN-mr, ESD

Abstract

The technical paper discusses the reduction of high leakage current failures of semiconductor IC (integrated circuit) packages by eliminating the ESD (electrostatic discharge) events during assembly process and ensuring the appropriate machine grounding and ESD controls.  It is imperative to reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding.  After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm.

References

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F.R. Gomez and T. Mangaoang Jr., “Elimination of ESD events and optimizing waterjet deflash process for reduction of leakage current failures on QFN-mr leadframe devicesâ€, Journal of Electrical Engineering, David Publishing Co., vol. 6, no. 4, pp. 238-243, July 2018.

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T. Mangaoang Jr., F.R. Gomez, and D. Burguillos Jr., “Reduction of leakage current failures on QFN-mr devices through DMAIC methodologyâ€, Presented at the 27th ASEMEP Technical Symposium, Manila, Philippines, June 2017.

M. Sato, “Static electricity handbookâ€, The Institute of Electrostatics Japan, Ohmsha, Ltd.

R.D. Mosbarger, and D.J. Hickey, “The effects of materials and post-mold profiles on plastic encapsulated circuitsâ€, In Proceedings of 1994 IEEE International Reliability Physics Symposium, San Jose, California, USA, April 1994.

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Published

2018-10-19

How to Cite

Gomez, F. R. (2018). Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events. Asian Journal of Engineering and Technology, 6(5). https://doi.org/10.24203/ajet.v6i5.5464

Issue

Vol. 6 No. 5 (2018): October 2018

Section

Articles

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