Package Design Optimization with Reliability Test Verification for Reduction of Voids and Delamination

Frederick Ray I. Gomez, Rammil A. Seguido

Abstract


Package down-scaling or miniaturization has become the trend in semiconductor industry, with smaller and thinner package being the prime objective.  Stacked dice process in semiconductor packages is now also becoming popular as semiconductor industries try to come up with products that offer multiple channels in a small IC (integrated circuit) package.  However, as different dice are brought together, several challenges have to be overcome in terms of package design and assembly.

This technical paper specifically considers the challenges encountered in the development of a compact and thinner package that incorporates multiple or stacked dice in one.  For the case of this paper, Die1 is smaller than Die2 and must be the first one to be die bonded, making the internal construction an unbalanced stacked dice.  Normally, stacked dice is in pyramid layout, wherein a single large die supports smaller top die.  Nevertheless, success is measured when there is a solution to control die attach voids and eliminate or significantly minimize delamination for unbalanced stacked dice as mentioned.  Ultimately, the paper presents the understanding of the factors involved and the package design optimization approach used to produce a successful unbalanced stacked die in a thin package using thin substrate.

Keywords


Semiconductor package; planarized; stacked dice

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References


K. Gilleo, “Area array packaging handbook – manufacturing and assembly”, 1st ed., McGraw-Hill Professional, New York, USA, November 2001.

W.J. Greig, “Integrated circuit packaging, assembly and interconnections”, 1st ed., Springer, USA, March 2007.

C. Chew and C.K. Tan, “Substrate design and process optimization of LGA (BT-based) package”, International Conference on Electronic Materials and Packaging, Toronto, Canada, pp. 1-10, December 2006.

S.N. Song, H.H. Tan, and P.L. Ong, “Die attach film application in multi die stack package”, 7th Electronics Packaging Technology Conference, Singapore, vol. 2, pp. 848-852, December 2005.

C.L. Chung, S.L. Fu, T. Lin, A. Lu, M. Ho, D. Kuo, and S. Chou, “A study on the characteristic of UV cured die-attach films in stack CSP (chip scale package)”, 12th IEEE International Conference on Microelectronics, Cairo, Egypt, pp. 365-368, December 2003.

Y. Su, D. Bai, V. Huang, W. Chen, and T.S. Xian, “Effect of transfer pressure on die attach film void performance”, 11th Electronics Packaging Technology Conference, Singapore, pp. 754-757, December 2009.

I. Ahmad, N.N. Bachok, N.C. Chiang, M.Z.M. Talib, M.F. Rosle, F.L.A. Latip, and Z.A. Aziz, “Evaluation of different die attach film and epoxy pastes for stacked die QFN package”, 9th Electronics Packaging Technology Conference, Singapore, pp. 869-873, December 2007.

E. Angeles, R. Seguido, and F.R. Gomez, “Elimination of voids and delamination in unbalanced stacked dice by optimizing substrate design”, Presented at the 23rd ASEMEP National Technical Symposium, Manila, Philippines, June 2013.

E. Angeles, R. Seguido, and F.R. Gomez, “Support structure for stacked integrated circuit dies”, US Patent No. US9258890B2, February 2016.




DOI: https://doi.org/10.24203/ajet.v6i6.5604

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