Package Design Optimization with Reliability Test Verification for Reduction of Voids and Delamination
DOI:
https://doi.org/10.24203/ajet.v6i6.5604Keywords:
Semiconductor package, planarized, stacked diceAbstract
Package down-scaling or miniaturization has become the trend in semiconductor industry, with smaller and thinner package being the prime objective. Stacked dice process in semiconductor packages is now also becoming popular as semiconductor industries try to come up with products that offer multiple channels in a small IC (integrated circuit) package. However, as different dice are brought together, several challenges have to be overcome in terms of package design and assembly.
This technical paper specifically considers the challenges encountered in the development of a compact and thinner package that incorporates multiple or stacked dice in one. For the case of this paper, Die1 is smaller than Die2 and must be the first one to be die bonded, making the internal construction an unbalanced stacked dice. Normally, stacked dice is in pyramid layout, wherein a single large die supports smaller top die. Nevertheless, success is measured when there is a solution to control die attach voids and eliminate or significantly minimize delamination for unbalanced stacked dice as mentioned. Ultimately, the paper presents the understanding of the factors involved and the package design optimization approach used to produce a successful unbalanced stacked die in a thin package using thin substrate.References
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