FPGA Implementation of Advance Encryption Standard Using Xilinx System Generator
Keywords:AES, System Generator, FPGA, Cryptography
This paper presents a resource efficient reconfigurable hardware implementation of Advance Encryption Standard (AES) algorithm using High Level Language (HLL) approach on Field Programmable Gate Array (FPGA) for rapid development. In this work, we use an approach to directly map the design described in a high level package i.e. System Generator on FPGA platforms. This approach is ideal for Encryption functions where the development of data-path architectures can easily be done to provide bit and cycle accurate models. Our approach fills the gap between performance and flexibility by efficiently applying re-configurability. We use primitive level approach and customize all the operations our design by effectively utilizing conventional blocks of Xilinx System Generator to get optimum performance in terms of speed and area. This approach enables us to minimize critical paths in design and increase the overall frequency of design especially for MixColumn and SubByte transform. Our design shows best performance in terms of speed and area as compared with any other software and hardware/software co-design implementation counterparts, it operates at 288.19 MHZ and offers high throughput of 36.864 Gbps.
N. A. Saqib, C. K. Koc, A .D. PÃ©rez, F. Rodriguez-Henriquez, â€œCryptographic Algorithms on Reconfigurable Hardwareâ€, Signals and Communication Technology, Springer, vol. 26, pp. 362, 2007.
M. Mozaffari-Kermani, A. Reyhani-Masoleh, "Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM," IEEE Transactions on Computers, vol. 61, no. 8, pp. 1165-1178, Aug. 2012.
E. El-Araby, Saumil G. Merchant, T. El-Ghazawi, "A Framework for Evaluating High-Level Design Methodologies for High-Performance Reconfigurable Computers," IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 1, pp. 33-45, Jan. 2011.
M. Mali, F. Novak and A. Biasizzo, â€œHardware Implementation of AES Algorithmâ€, Journal of Electrical Engineering, vol. 56, pp 265â€“269, 2005.
M. Askar and T. Egemen, â€œDesign and SystemC Implementation of a Crypto Processor for AES and DES Algorithmsâ€, Information Security and Cryptology Conference with International Participation, Dec 2007.
M. Lukowiak, S. Radziszowski and J. Vallino and C. Wood, â€œCybersecurity Education: Bridging the Gap Between Hardware and Software Domainsâ€.
F. Oboril, I. Sagar, M. B. Tahoori, "A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES", On-Line Testing Symposium (IOLTS), IEEE 19th International, pp.104-109, 8-10 July 2013.
Y. Wang, Y. Ha, "FPGA-Based 40.9-Gbits/s Masked AES with Area Optimization for Storage Area Network", Circuits and Systems II: Express Briefs, IEEE Transactions, vol.60, no.1, pp.36-40, Jan 2013.
D. Osvik, J. Bos, D. Stefan and D. Canright, â€œFast Software AES Encryptionâ€, FSE'10 Proceedings of 17th International Conference on Fast Software Encryption, pp 75-93, 2010.
T. Babu, K. Murthy and G. Sunil, â€œAES Algorithm Implementation using ARM Processorâ€, 2nd International Conference and workshop on Emerging Trends in Technology (ICWET) Proceedings published by International Journal of Computer Applications (IJCA), 2011
M. Hasamnis, P. Jambhulkar and S. Limaye, â€œImplementation of AES as a Customâ€, Advanced Computing: An International Journal (ACIJ), vol.3, No.4, July 2012.
J. Bos, D. Osvik, D. Stefan, â€œFast Implementations of AES on Various Platformsâ€, IACR Cryptology ePrint Archive, vol. 501, 2009.
M. Biglari, E. Qasemi, B. Pourmohseni, "Maestro: A high performance AES encryption/decryption system", Computer Architecture and Digital Systems (CADS), 17th CSI International Symposium, pp.145-148, 30-31 Oct. 2013.
O. Mourad, S. Lotfy, M. Noureddine, B. Ahmed, T. Camel, "AES Embedded Hardware Implementation", Adaptive Hardware and Systems, Second NASA/ESA Conference, pp.103-109, 5-8 Aug. 2007.
FIPS-197, â€œFederal Information Processing Standards Publication FIPS-197, Advanced Encryption Standard (AES)â€, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf, October 1999.
N.Anitha Christy and P.Karthigaikumar, â€œFPGA Implementation of AES Algorithm using Composite Field Arithmeticâ€, International Conference on Devices, Circuits and Systems (ICDCS), pp. 713-717, 2012.
A. C. Zigiotto, R. d'Amore, "A Low-Cost FPGA Implementation of the Advanced Encryption Standard Algorithm," 15th Symposium on Integrated Circuits and Systems Design, pp.191, 2002.
S. Qu, G. Shou, Y. Hu, Z. Guo and Z. Qian, â€œHigh Throughput Pipelined Implementation of AES on FPGAâ€, International Symposium on Information Engineering and Electronic Commerce, pp. 542-545, 2009.
V. Elamaran and G. Rajkumar, â€œFPGA Implementation of Point Processes Using Xilinx System Generatorâ€, Journal of Theoretical and Applied Information Technology, vol. 41,pp. 201-206, July 2012.
How to Cite
- Papers must be submitted on the understanding that they have not been published elsewhere (except in the form of an abstract or as part of a published lecture, review, or thesis) and are not currently under consideration by another journal published by any other publisher.
- It is also the authors responsibility to ensure that the articles emanating from a particular source are submitted with the necessary approval.
- The authors warrant that the paper is original and that he/she is the author of the paper, except for material that is clearly identified as to its original source, with permission notices from the copyright owners where required.
- The authors ensure that all the references carefully and they are accurate in the text as well as in the list of references (and vice versa).
- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Attribution-NonCommercial 4.0 International that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
- The journal/publisher is not responsible for subsequent uses of the work. It is the author's responsibility to bring an infringement action if so desired by the author.